This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-076350, filed Mar. 19, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a wiring structure of a semiconductor device and a method of fabricating the same, and particularly to a technique of preventing a crack from being generated in an inter-level insulating film under an electrode pad when a connecting member, such as a wire or a bump, is bonded to the electrode pad.
In recent years, in order to allow LSIs to operate at a higher speed, an insulating film having a lower dielectric constant is used as an inter-level insulating film. For this reason, a silicon oxide film containing an organic substance formed by means of an SOG (Spin-On-Glass) method, which will be referred to as an SOG film or layer, has come into use as an inter-level insulating film, in place of an SiO2 film formed by means of a CVD (Chemical Vapor Deposition) method, such as a silicon oxide film formed by using TEOS (tetraethyl orthosilicate), which is referred to as a TEOS film or layer. This is because the SOG film has a dielectric constant lower than that of the TEOS film.
However, the SOG film has a mechanical strength lower than the TEOS film, and has a hardness about one tenth that of the TEOS film. Furthermore, the TEOS film is formed to have a compressive stress. On the other hand, the SOG film has a coefficient of linear expansion higher than that of an Si substrate, and thus the SOG film is formed to have a tensile stress, by means of a present film-formation method with no stress control. Under such circumstances the organic SOG film is apt to easily generate a crack when pressure is applied to the film.
This problem appears most seriously in a step of bonding a connecting member, such as a wire, a bump, or an anisotropic conductivity sheet, to an electrode pad. Specifically, due to pressure applied to the electrode pad during the bonding, a crack is generated in an SOG film directly under the pad. In this respect, FIGS. 10A to 10F are cross-sectional views showing steps of a conventional method of fabricating a wiring structure of a semiconductor device.
First, as shown in FIG. 10A, a wiring layer 2 is formed on an insulating layer 1, and, then, is covered with an organic SOG layer 3. Then, as shown in FIG. 10B, a via hole 4 relative to the wiring layer 2 is formed in the SOG layer 3. Then, Al is deposited over the resultant structure to form an Al film 5 on the SOG layer 3 and in the via hole 4.
Then, as shown in FIG. 10C, the Al film 5 is patterned to form an Al electrode pad 6 by means of lithography and a following RIE (Reactive Ion Etching) method. Then, as shown in FIG. 10D, a passivation layer 7 consisting of, e.g., an organic SOG film, a plasma CVD silicon oxide film, or a plasma CVD silicon nitride film, is formed over the resultant structure.
Then, as shown in FIG. 10E, a through hole 8 is formed in the passivation layer 7 to expose the Al pad 6. Thereafter, dicing and mounting are performed for assembling, and, then, as shown in FIG. 10F, wire bonding is performed relative to the Al pad 6. At this time, a wire 9 is brought into close contact with the Al pad 6 such that pressure is applied to the pad 6, whereby the wire 9 is connected to the pad 6.
In this wire bonding process, a problem arises in that a crack is generated in the SOG layer 3 directly under the pad 6.
An object of the present invention is to provide a wiring structure of a semiconductor device and a method of fabricating the same which allow an inter-level insulating film to have a lower dielectric constant, and which, on the other hand, prevent a crack from being generated in the inter-level insulating film under an electrode pad when a connecting member, such as a wire, is bonded to the electrode pad.
According to a first aspect of the present invention, there is provided a wiring structure of a semiconductor device comprising:
a wiring layer arranged on a substrate;
an inter-level insulating film covering the wiring layer and having a via hole formed to correspond to the wiring layer;
a conductive via plug arranged in the via hole; and
an electrode pad arranged on the inter-level insulating film and electrically connected to the wiring layer by the via plug;
wherein the inter-level insulating film comprises a first insulating layer having a relative dielectric constant of 3.0 or less, and a Young""s modulus of less than 50 GPa, and a second insulating layer having a Young""s modulus of 50 GPa or more, and intervening between the first insulating layer and the electrode pad.
According to a second aspect of the present invention, there is provided a wiring structure of a semiconductor device comprising:
a plurality of wiring layers arranged at different levels on a substrate;
a plurality of first insulating layers covering the wiring layers of the different levels, respectively, and having via holes formed to correspond to the wiring layers, respectively, the first insulating layers each having a relative dielectric constant of 3.0 or less, a Young""s modulus of 10 GPa or less, and a density of less than 2.0 g/cm3;
conductive via plugs arranged in the via holes, respectively;
an electrode pad arranged on an uppermost first insulating layer located at an uppermost position among the fist insulating layers, and electrically connected to one of the wiring layers by one of the via plugs; and
a second insulating layer intervening between the uppermost first insulating layer and the electrode pad, and having a Young""s modulus of 50 GPa or more.
According to a third aspect of the present invention, there is provided a wiring structure of a semiconductor device comprising:
a plurality of wiring layers arranged at different levels on a substrate;
a plurality of first insulating layers arranged at levels substantially the same as those of the wiring layer of the different levels to surround the wiring layers, respectively, the first insulating layers each having a relative dielectric constant of 3.0 or less, a Young""s modulus of 10 GPa or less, and a density of less than 2.0 g/cm3;
a plurality of second insulating layers arranged to cover the wiring layers and the first insulating layers of the different levels, respectively, and having via holes formed to correspond to the wiring layers, respectively, the second insulating layers each having a Young""s modulus of 50 GPa or more;
conductive via plugs arranged in the via holes, respectively; and
an electrode pad arranged on an uppermost second insulating layer located at an uppermost position among the second insulating layers, and electrically connected to one of the wiring layers by one of the via plugs.
According to a fourth aspect of the present invention, there is provided a method of fabricating a wiring structure of a semiconductor device comprising:
covering a wiring layer arranged on a substrate with an inter-level insulating film which comprises a first insulating layer having a relative dielectric constant of 3.0 or less, and a Young""s modulus of less than 50 GPa, and a second insulating layer having a Young""s modulus of 50 GPa or more and staked on the first insulating layer;
forming a via hole in the inter-level insulating film to correspond to the wiring layer;
forming a conductive via plug in the via hole, and forming an electrode pad on the second insulating layer of the inter-level insulating film, such that the electrode pad is electrically connected to the wiring layer by the via plug; and
electrically connecting a connecting member to the electrode pad while applying pressure to the electrode pad.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.